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AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
V CC
V CC
R THRM
MAX17009
R THRM
MAX17009
PLACE R NTC NEXT TO THE
HOTTEST POWER COMPONENT.
R NTC
THRM
PLACE R PTC1 AND R PTC2
NEXT TO THE RESPECTIVE
PHASE'S POWER COMPONENT.
R PTC1
THRM
GND
GND
Figure 8. THRM Configuration
VRHOT Temperature Comparator
The MAX17009 features an independent comparator
with an accurate threshold (V HOT ) that tracks the ana-
log supply voltage (V HOT = 0.3 x V CC ). Use a resistor-
and thermistor-divider between V CC and GND to gene-
rate a voltage-regulator overtemperature monitor. Place
the thermistor as close to the MOSFETs and inductors
as possible.
For combined-mode operations, the current-balance
circuit balances the currents between phases. As such,
the power loss and heat in each phase should be iden-
tical, apart from the effects of placement and airflow
over each phase. A single thermistor can be placed
near either of the phases and still be effective.
For separate mode operation, the load currents between
phases may be very different. Using two “logic-level”
thermistors (e.g., Murata PRF series POSITORS) allows
the same VRHOT comparator to monitor the tempera-
ture of both phases. Figure 8 is the THRM configuration.
Fault Protection (Latched)
P R O Selectable Overvoltage
Protection and Debug Mode
The MAX17009 features a tri-level PRO pin that enables
the overvoltage protection feature, or puts the MAX17009
in debug mode. Table 5 shows the PRO -selectable
options. Debug mode is intended for applications where
the serial interface is not properly functioning, and the
output voltage needs to be adjusted to different levels.
The DAC voltage settings in debug mode further depend
on the PGD_IN level to switch between the 2-bit VID
setting or the serial interface operation.
Table 5. PRO Settings
PRO DESCRIPTION
R PTC2
Output Overvoltage Protection
The overvoltage-protection (OVP) circuit is designed to
protect the CPU against a shorted high-side MOSFET
by drawing high current and blowing the battery fuse.
The MAX17009 continuously monitors the output for an
overvoltage fault. The controller detects an OVP fault if
the output voltage exceeds the set VID DAC voltage by
more than 300mV. The OVP threshold tracks the VID
DAC voltage except during a downward VID transition.
During a downward VID transition, the OVP threshold is
set at 1.80V (min), until the output reaches regulation,
when the OVP threshold is reset back to 300mV above
the VID setting.
When the OVP circuit detects an overvoltage fault, it
immediately forces the external low-side driver high on
the faulted side and initiates the soft-shutdown for the
other SMPS and the NBV_BUF. The synchronous-recti-
fier MOSFETs of the faulted side are turned on with
100% duty, which rapidly discharges the output filter
capacitor and forces the output low. If the condition
that caused the overvoltage (such as a shorted high-
side MOSFET) persists, the battery fuse blows. Toggle
SHDN or cycle the V CC power supply below 0.5V to
clear the fault latch and reactivate the controller.
When in combined mode, the synchronous-rectifier
MOSFETs of both phases are turned on with 100% duty
in response to an overvoltage fault.
Overvoltage protection can be disabled by setting PRO
to high or open.
Output Undervoltage Protection
The output UVP function is similar to foldback current
limiting, but employs a timer rather than a variable cur-
rent limit. If the MAX17009 output voltage is 400mV
below the target voltage, the controller activates the
shutdown sequence for both SMPS and NBV_BUF, and
V CC
OPEN
GND
OVP disabled
Debug mode, OVP disabled
OVP enabled
sets the fault latch. Toggle SHDN or cycle the V CC
power supply below 0.5V to clear the fault latch and
reactivate the controller.
______________________________________________________________________________________
33
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